Half-Adder circuit discussion with Verilog code.

Half-adder is represented in the diagram below. Its used to calculate sum of two 1 bit inputs using a circuit composed of one AND gate and one XOR gate.

Half Adder

The equations for sum_out and sum_carry are discussed below.

sum_out = in_x XOR in_y,

carry_out = in_x AND in_y

LTE - 4G Wireless Technology

Digital fundamentals.

Interview Questions.

Lets use equations from above to build truth table for Half-adder.

in_x in_y out_carry out_sum
0 0 0 0
0 1 0 1
1 0 0 1
1 1 1 0


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