Home.Verilog.Digital Design.Digital Basics.Python.RF Basics.
Previous.
Next.
Custom Search

Legal Disclaimer

Chip Designing for ASIC/ FPGA Design engineers and Students
FULLCHIPDESIGN
Digital-logic Design...  Dream for many students… start learning front-end…

Legal Disclaimer

@TYH :- 4G LTE Long Term Evolution Tutorial, CloudComputing
PICS
Verilog Tutorial.
Get Noticed:- Submit your own content to be published on fullchipdesign.com

Send it to fullchip@gmail.com

Digital Basics Tutorial.

4 - variable Karnaugh map (K-map)

Truth Table

4 variable K– map for the truth -table above.

 

K-map location Number

 

 

x

 

 

y

 

 

z

 

 

w

 

 

Output Function

 

 

0

 

 

0

 

 

0

 

 

0

 

 

0

 

 

x’y’z’w’

 

 

1

 

 

0

 

 

0

 

 

0

 

 

1

 

 

x’y’z’w

 

 

2

 

 

0

 

 

0

 

 

1

 

 

0

 

 

x’y’zw’

 

 

3

 

 

0

 

 

0

 

 

1

 

 

1

 

 

x’y’zw

 

 

4

 

 

0

 

 

1

 

 

0

 

 

0

 

 

X’yz’w’

 

 

5

 

 

0

 

 

1

 

 

0

 

 

1

 

 

x’yz’w

 

 

6

 

 

0

 

 

1

 

 

1

 

 

0

 

 

x’yzw’

 

 

7

 

 

0

 

 

1

 

 

1

 

 

1

 

 

x’yzw

 

 

8

 

 

1

 

 

0

 

 

0

 

 

0

 

 

xy’z’w’

 

 

9

 

 

1

 

 

0

 

 

0

 

 

1

 

 

xy’z’w

 

 

10

 

 

1

 

 

0

 

 

1

 

 

0

 

 

xy’zw’

 

 

11

 

 

1

 

 

0

 

 

1

 

 

1

 

 

xy’zw

 

 

12

 

 

1

 

 

1

 

 

0

 

 

0

 

 

xyz’w’

 

 

13

 

 

1

 

 

1

 

 

0

 

 

1

 

 

xyz’w

 

 

14

 

 

1

 

 

1

 

 

1

 

 

0

 

 

xyzw’

 

 

15

 

 

1

 

 

1

 

 

1

 

 

1

 

 

xyzw

 

00

01

11

10

 

3

 

 

2

 

xy

zw

00

01

11

10

 

4

 

 

5

 

 

7

 

 

6

 

 

12

 

 

13

 

 

15

 

 

14

 

 

8

 

 

9

 

 

10

 

 

11

 

 

0

 

 

1

 

Binary Numbers 1s_complement 2s_complement Binary Subtraction Binary Sub. Ex's Sign_magnitude SignM EX Gray Coding BCD coding Digital gates NAND NOR & XNOR Theorems Boolean Functions BFunc Examples Minterm Maxterm Sum of Minterms Prdt of Maxterms 2 var K-map 3 var K-map 4 var K-map 5 var K-map Prime Implicant PI example K-map Ex's KMap minimization 2 var EX
Interview Questions. Main, FPGA, Digital Fundamentals
Four variable K-Map minimization examples.
1. F(x,y,w, z) = (0,1,2,3,4,6,11,14)
2. F(x,y,w, z) = (0,2,4,6,12,14)
3. F(x,y,w, z) = (0,2,5,7,8,11,13,15)

K-map for 4 variables x,y,z,w is discussed below with truth table and k-map plot. Also discussed are some examples.

3 var K-map.
5 var K-map.

SystemVerilog

Parameters passing, defparam & localparam

Alias, Array, Assertions

 

LTE - Long Term Evolution topics from here