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Verilog Tutorial.
Binary Numbers 1s_complement 2s_complement Binary Subtraction Binary Sub. Ex's Sign_magnitude SignM EX Gray Coding BCD coding Digital gates NAND NOR & XNOR Theorems Boolean Functions BFunc Examples Minterm Maxterm Sum of Minterms Prdt of Maxterms 2 var K-map 3 var K-map 4 var K-map 5 var K-map Prime Implicant PI example

Karnaugh map or K-map discussion

It is a way of minimizing the Boolean functions using diagrams which are made up of squares. By minimization we imply a function with minimum number of terms and each term with lowest number of literals.

Following sub-topics are discussed in this section:

1) Two variables K-map

2) Three variables K-map

3) Four variables K-map

4) Five variables K-map

5) Prime Implicant and Gate level minimization examples

2 -Variable Karnaugh map (K-map) discussion below

Truth Table for 2 variables x and y

2 variable K– map plot below

K-map location number
x
y
Output function
0
0
0
x’y’
1
0
1
x’y
2
1
0
xy’
3
1
1
xy

0

1

0

1

x

y

x’y’
x’y
xy’
xy
Misc. Verilog RTL examples:-

Binary to Gray Code conversion
 File read write operations.
 Clock domain crossing.
 Half-adder, Full-adder, Tri-state buffer .
 Verilog testbench to validate half-adder, full-adder and tri-state buffer.
VERILOG HOME
Interview Questions.

Main, FPGA, Digital Fundamentals
Resources
 Clock Domain Crossing Discussion with rtl & testbench example.
Rate change(asynchronous) FIFO design and fifo depth calculation.
Half-adder, Full-adder, 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT
 Arithmetic, logical, shift micro-operations. Stack organization, LIFO, RPN discussion.
 RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow.
 Guide to Graduate studies in US
 Pipeline vs. Parallel processing.