The technology library has dedicated specifications in terms of operating voltage,
area & operating conditions like temperature. Required wireload, in/out timings and
logical symbols are also part of technology library.
All digital design ASIC or FPGA’s consists of digital routes for signal propagation.
These routes are mostly from flop-to-flop, input-to-flop or flop-to-output. The synthesis
tools needs to understand the timing requirements for these routes. Also from flops
we need to define clocks in the design. Other requirements to time in/out ports
involve set_input_delay and set_output_delays. Many other requirements are part of
digital synthesis constraints.