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Chip Designing for ASIC/ FPGA Design engineers and Students
Digital-logic Design...  Dream for many students… start learning front-end…

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Role of Synthesis in Digital chip design.

Synthesis: Its a technique automated by EDA tools to map high level behavioral designs coded with help of Register Transfer Level languages into gates. These gates are distributed over an area and connected with wires. These synthesized gate level abstraction or net lists are then optimized in several steps to attain faster speed, low area, low power and test-ability.  






Read in Technology library

Read in RTL behavioural design

Read in design constraints

Synthesis: Pre-possessing of the design. (Syntax check, compile and elaboration.)

Logic minimization and optimization in terms of Boolean Logic.


Mapping of minimized logic to technology library elements.


Post processing of Mapped design. (Constraint validation and re-optimization)



Net-list (Structural Design)

VLSI Synthesis for Digital Logic

In short, synthesis is used to port RTL design to gate level design. The steps are also shown pictorially below.

Interview Questions. Main, FPGA, Digital Fundamentals
Interview Questions. Main, FPGA, Digital Fundamentals

Various stages of EDA synthesis are discussed on next page. Link here  

Synth Stags.
LTE - Long Term Evolution topics from here