Synthesis: Its a technique automated by EDA tools to map high level behavioral designs
coded with help of Register Transfer Level languages into gates. These gates are
distributed over an area and connected with wires. These synthesized gate level abstraction
or net lists are then optimized in several steps to attain faster speed, low area,
low power and test-ability.
Read in Technology library
Read in RTL behavioural design
Read in design constraints
Synthesis: Pre-possessing of the design. (Syntax check, compile and elaboration.)
Logic minimization and optimization in terms of Boolean Logic.
Mapping of minimized logic to technology library elements.
Post processing of Mapped design. (Constraint validation and re-optimization)