Design rule constraints are provided as part of technology library and it specifies
load capacitance, number of maximum load elements or fanout, maximum transition time,
cell degradation etc. Link with more details.
Design Optimization constraints comprise of all constraints defined by designer.
Some of those constraints are discussed below. Define, master clocks, derived clocks,
Input/output chip port timing delays, false paths and multi-cycle paths etc.
Constraints are derived from timing specifications of the design and it provides
critical information to synthesis EDA tools to limit minimum or maximum delays for
different datapath, clocks etc. on the hardware.