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Home Memory Dis Cache Memory Associative Cache Cache Hardware Cache control ACache arch Memory Array Direct Mapped Cache Direct Mapped D
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Associative cache memory hardware match circuitry.
We have already discussed Cache line and TAG memory and various control flags in previous sections. To implement an efficient control circuit in hardware requires following approach.  

Implement a comparison circuit to match value in tag locations to the TAG field in address register. The control circuit needs to have an argument register to temporarily store TAG bits from address register.  
In the above circuit the location X in tag memory corresponds to location within cache memory where the comparison is performed. In hardware we will need to implement P such blocks in parallel for each cache line.  The output of the circuit is going to be ‘1’ only when all the bits in argument register matches to corresponding bit in tag memory location.
When the output of above circuit is high then the corresponding bit in ‘match’ control flag is set to ‘1’. The circuit can be implemented simply by using XOR and NOR gates.  
LTE - Long Term Evolution topics from here
Interview Questions. Main, FPGA, Digital Fundamentals
TAG memory location x
[13:0] total 14 lines
Match X location = 1
Control Circuit for generating a match between address and TAG
Argument Register
Address[15:0] >> TAG[15:3] + OFFSET[3:0]
Interview Questions. Main, FPGA, Digital Fundamentals
Interview Questions.
Main, FPGA, Digital Basics
LTE - Long Term Evolution topics from here
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