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Home Memory Dis Cache Memory Associative Cache Cache Hardware Cache control ACache arch Memory Array Direct Mapped Cache Direct Mapped D
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Cache Memory complete hardware block diagram discussed above.
Associative cache memory complete hardware circuit.
We have already discussed Cache line and TAG memory and various control flags in previous sections. To implement an efficient control circuit in hardware requires following approach.  
Implement a comparison circuit to match value in tag locations to the TAG field in address register. The control circuit needs to have an argument register to temporarily store TAG bits from address register.  
When the output of above circuit is high then the corresponding bit in ‘match’ control flag is set to ‘1’. The complete circuit can be implemented simply by using AND gate, a buffer and a multiplexer for each cache line.  
LTE - Long Term Evolution topics from here
Interview Questions. Main, FPGA, Digital Fundamentals
Block Nos (TAG)
No of Bytes (offset)
Any 1 of 8192 = (2^13)
Any 1 of 8 = (2^3)
Cache line 0 (upto8 bytes)
Cache line 1
Cache line 2
....
....
Cache line P
Tag 0
Tag 1
Tag 2
....
....
Tag P
Match circuit from previous topic.
MULTIPLEXER
Data to Processor
Interview Questions.
Main, FPGA, Digital Fundamentals
LTE - Long Term Evolution topics from here