Home Verilog Digital Design Digital Basics Python RF Basics

Legal Disclaimer

Chip Designing for ASIC/ FPGA Design engineers and Students
FULLCHIPDESIGN
Digital-logic Design...  Dream for many students… start learning front-end…
Custom Search

Feedback ? Send it to admin@fullchipdesign.com or join me at fullchip@gmail.com

Digital Design Clock Crossing Async FIFO Half Adder Full Adder Binary Adder Overflow Overflow Det Adder-Subtractor Multiplier Parity check RTL guidelines NAND to INVERTER VHDL RTL Arith Micro-ops Stack Org Parallel proc. Pipeline proc CMOS Intro

Legal Disclaimer

Topics @TYH :- 4G LTE Tutorial, GVIM editor, Smart-Phone, Cloud Computing
Previous Next
Verilog Tutorial.
Digital Basics Tutorial.
Example Overflow in signed magnitude.
Overflow introduction & scenarios click here.

Example: Signed magnitude number

Add two sign magnitude numbers -70 & -90  with previous carry = 0.
Sol. Load the values in two 8 bit registers R1 and R2.
So, R1 = -70 (decimal)
&   R2 = -90 (decimal)

The detailed steps to calculate results are listed in table below:-
Register
Value (in decimal)
Value (in Hex)
Value (in decimal)
Value (in 2’s complement)
R1
-70
-46
1 100 0110
   1 011 1010
R2
-90
-5A
1 101 1010
   1 010 0110
Result
Carry
1   0110 0000   
Following are the rules for overflow condition detection in signed magnitude.
1. For signed numbers leftmost bit always represents sign.
2. Is there a carry into sign bit position?
3. Is there a carry out of sign bit position?
4. If step 2 and step 3 results are not equal then the overflow condition is detected.
Table to list four steps to add registers R1 and R2. Result is shown in column 5.
PICS
Lets apply the rules to our example:-
Statement 2 is false and statement 3 is true. So we have an overflow.
 
So the final result is:-
Carry bit = sign
Sum = 2’s complement of 8 bits

1 1010 0000 = 1A0 (in hex) = -160 (decimal)

We need an extra flop to store the overflow bit.  

Other examples:-
Overflow in adding two positive numbers

Overflow in adding a positive number to a negative number.
Interview Questions. Main, FPGA, Digital Fundamentals