Chip Designing for ASIC/ FPGA Design engineers and Students

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Computer Organization.
Memory Organization.
Cache Organization.
Interrupt controller.

Example Overflow in signed magnitude.

Overflow introduction & scenarios click here.

Example: Signed magnitude number

Add two sign magnitude numbers -70 & -90  with previous carry = 0.
Sol. Load the values in two 8 bit registers R1 and R2.
So, R1 = -70 (decimal)
&   R2 = -90 (decimal)

The detailed steps to calculate results are listed in table below:-

Following are the rules for overflow condition detection in signed magnitude.
1. For signed numbers leftmost bit always represents sign.
2. Is there a carry into sign bit position?
3. Is there a carry out of sign bit position?
4. If step 2 and step 3 results are not equal then the overflow condition is detected.

Table to list four steps to add registers R1 and R2. Result is shown in column 5.

Resources
Digital design resources
Clock Domain Crossing rtl & testbench.
Rate change (asynchronous) FIFO design and fifo depth calculation.
Half-adder, Full-adder, 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT, Arithmetic, logical, shift micro-operations. Stack organization, LIFO, RPN discussion.
RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow.
Guide to Graduate studies in US
Pipeline vs. Parallel processing.

Misc. Verilog RTL examples:-

Binary to Gray Code conversion
File read write operations.
Clock domain crossing.
Half-adder, Full-adder, Tri-state buffer .
Verilog testbench to validate half-adder, full-adder and tri-state buffer.
VERILOG HOME

Binary adder-subtractor circuit

Lets apply the rules to our example:-
Statement 2 is false and statement 3 is true. So we have an overflow.
 
So the final result is:-
Carry bit = sign
Sum = 2’s complement of 8 bits

1 1010 0000 = 1A0 (in hex) = -160 (decimal)

We need an extra flop to store the overflow bit.  

Other examples:-
Overflow in adding two positive numbers

Overflow in adding a positive number to a negative number.

Interview Questions. Main, FPGA, Digital Fundamentals

Arithmetic, logical, shift micro-operations, Overflow