# Generating random numbers and $fdisplay in Verilog testbench.

Verilog testbench to generate random numbers and use of $fdisplay to store it in a text file.

// Test Bench for generating random numbers module random_tb (); integer seed; integer out; integer i ; initial begin out = $fopen("rand.vec","w"); $fdisplay(out, "seed = %h, 1st random number in hexadecimal = 0x%h", seed, $random(seed)); $fdisplay(out, "seed = %h, 2nd random number in hexadecimal = 0x%h", seed, $random(seed)); $fdisplay(out, "seed = %h, 3rd random number in hexadecimal = 0x%h", seed, $random(seed)); $fdisplay(out, "seed = %h, 4th random number in hexadecimal = 0x%h", seed, $random(seed)); $fdisplay(out, "seed = %h, 5th random number in hexadecimal = 0x%h", seed, $random(seed)); end endmodule