Verilog Function declaration and call.
Verilog functions are used to simplify coding in presence of lengthy, complex and repetitive code. Functions are used to group code segments which can then be used multiple (no limit) times. Terms used in example code below are Function Declaration and Function Call.
Properties of functions:
(1) Can only be used to pass one argument to/from function.
(2) Function code segments with latches will not get interpreted during synthesis. So avoid latches in function code to prevent simulation/synthesis mis-