Verilog Case construct.

Verilog “case” statements are used to model states in Finite State Machine.

Its also used to generate conditional statements based on value of a register. Case statement implementation is shown below in two examples below.

~\Documents\fullchip\python\mysite\webpages\templates\webpages\test.v.html

module casecode (
                in_a,
                in_b,
                in_ctrl,
                out_c
        );
        // Define inputs/outputs
        input  in_a;
        input  in_b;
        input  in_ctrl;
        output out_c;
        // Use of case statement. 
        always@(*)
        begin
         case(in_ctrl)
                1 : out_c = in_b;
                default: out_c = in_a;
         endcase
        end
endmodule

Verilog case construct above is a simple multiplexor to select one of two inputs and assign it to output c. Verilog 2001 onwards we can use * operator to list all variables of senstivity list of always block. Also note the use of default statement in verilog case is to avoid inferring of latches. The default statement ensures a known logic value for output at all unknown states.

To handle ‘z’ and ‘x’ states, different variations of case statement are used.

casez : Treats z as don't care.

casex : Treats x and z as don't care.

SystemVerilog case statement construct is similar to verilog.