Modular coding and
Parameters in Verilog
modular coding style?
What are parameters?
The verilog parameters is a way of passing the
level/higher- level module. Parameters also allows easy modifications of the code by changing the values outside of the code.
constants to modules to overwrite there local constants for signal widths and depths (for memories). This is done when the block is
instantiated in top-
Code snippet from the verilog sync ram page is below: