Verilog FOR loop. Can it be used to design hardware?
Following example shows the declaration of Verilog FOR loop.
for (i=0; i < 4; i=i+1)
$display("%d:%h", i, data[i]);
Commonly asked questions for Verilog and SystemVerilog are listed below.
Question. Can we synthesize FOR loops to
replicatehardware or fpga ?
Question. Is it valid or smart coding style to freely use FOR loops in RTL? Can we do increment using for loops? (yes)
Answer to above questions is elaborated below:
First of all
FOR loopis completely
synthesizableconstruct. These are used when speed of digital hardware is critical and there is not much
limitationon hardware utilization. With FOR loops we are basically instantiating same hardware circuit multiple times.
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