Cache Memory Organization

In high speed computing data is made available to processors in small temporary memories know as Cache. These memories are placed much closer to the CPU in comparison to main memory available on the device.
Cache memory doesn’t act as permanent storage rather its transparent to processor. It primary operation is to act as temporary storage for high probability data for future memory accesses.

(1) Associative Cache Memory.

Only cache lines no cache pages involved. Any cache line from main memory can be placed at any location in cache. Lots of comparator are required.

Fully Associative Cache memory & TAG
Block diagram of fully-Associative Cache.
Address match circuitry Associative cache.
Complete hardware fully Associative cache.

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(2) Direct MappedCache Memory.
Direct Mapped (also known as 1-way set Associative): Fixed mapping of cache lines within a cache page from main memory to cache location. So one location in cache can only have one corresponding entry from main memory cache pages. less complex and also less efficient.

(3) Set-associative Cache Memory.
Set Associative (2 way or 4 way): Hybrid of above 5 architectures. Cache memory is partitioned into 2 or 4 equal parts called ways. Then we have 2/4 way full associative and each partition acts as direct mapped.

Cache memory has further classifications in terms of proximity to the processor.

L1 Cache- Its on the same chip as the microprocessor.
L2 Cache- Its usually on a separate static RAM (SRAM) chip.

Next topic : Associative Cache Memory


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