state buffer logic discussion.
We will discuss tri-
introduction followed by Verilog code to implement it at RTL level. Will also cover Inverting tristate buffer.
as a switch in digital circuit by isolating a signal path in a circuit. This switch can attain three logical states. The three states are 0, 1 and ‘Z’. The logical state 0 and 1 are possible when the switch is CLOSE. The logical value ‘Z’ or high impedance is attained when switch is OPEN. So when switch is open the input to tristate buffer is isolated from the circuit and output can be driven by some other logical path on a shared connection on a bus. Note an imporatant interview question.
Verilog RTL example for tri-
// Tristate Buffer
module tristate_buffer(input_x, enable, output_x);
assign output_x = enable? input_x : 'bz;
Output of above Tri-
input_x = 0, enable = 0, output_x = z
input_x = 1, enable = 0, output_x = z
input_x = 1, enable = 1, output_x = 1
input_x = 0, enable = 1, output_x = 0