Synthesis: Pre-possessing of the design. (Syntax check, compile and elaboration.)

We have already discussed first stage in previous topic:

Stage 1 (previous topic). Various inputs required to run EDA synthesis tool - RTL, Technology library and synthesis constraints.

Next Synthesis step, is to run pre-processing of digital design in EDA.

Stage 2. Pre-possessing of the design using Synthesis tool - The input rtl (verilog or vhdl) is then compiled by the synthesis tools to run syntax check and once passed then run elaboration on it.

LTE - 4G Wireless Technology

Digital fundamentals.

Interview Questions.

Elaboration is responsible to translate the design into a database of interlinked generic elements which are independent of design language. All the parameters in the design are processed. Also the linked design is checked for missing port connections and report it in the logs.

In next topic we will cover Constraints for digital design.


Verilog Tutorial.

LTE Tutorial.

Memory Tutorial.

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