Verilog Signed Magnitude rtl code.

Signed number is a way of representing positive & negative numbers in binary form where most significant bit(MSB) signifies sign. In signed number system the most significant bit (msb) bit signifies sign of all lower significant bit (lsb) bits for the number. More detailed signed addition discussion from here.

In discussion below, signed addition is compared against logical AND operation. Also check results below.

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Interview Questions.

module signed_tb ();

// Half-Adder
reg signed[3:0] A;
reg signed[3:0] B;
reg signed[4:0] sum;
reg signed[4:0] carry;
integer i;
integer out;

always @(*)
begin
  sum = A + B ;
  carry = A & B;
  $fdisplay(out, "A = %d, B= %d, Sum = %d, AND=%d", A, B, sum, carry);
  $fdisplay(out, "A = %b, B= %b, Sum = %b, AND=%b", A, B, sum, carry);
End

initial begin
out = $fopen("signed_arith.txt", "w");
 A = 4'hF;
B = 12;
#10 A = 4'he;
    B = 13;
#10 A = 4'hd;
    B = 10;
#10 A = -7;
    B = -6;
#10 A = 7;
    B = 6;
#10 A = 7;
    B = -6;
#10 A = -7;
    B = 6;
end
endmodule

Results of above code.

A = -1, B= -4, Sum = -5, AND= -4
A = 1111, B= 1100, Sum = 11011, AND=11100
A = -2, B= -3, Sum = -5, AND= -4
A = 1110, B= 1101, Sum = 11011, AND=11100
A = -3, B= -6, Sum = -9, AND= -8
A = 1101, B= 1010, Sum = 10111, AND=11000
A = -7, B= -6, Sum = -13, AND= -8
A = 1001, B= 1010, Sum = 10011, AND=11000
A = 7, B= 6, Sum = 13, AND= 6
A = 0111, B= 0110, Sum = 01101, AND=00110
A = 7, B= -6, Sum = 1, AND= 2
A = 0111, B= 1010, Sum = 00001, AND=00010
A = -7, B= 6, Sum = -1, AND= 0
A = 1001, B= 0110, Sum = 11111, AND=00000

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