and FPGA: PLL applications
Selecting a correct PLL earlier in design of ASIC, FPGA or SOC is critical.
ASIC clock generation: Generation of high frequency clocks from low frequency reference.
DDR (double data rate): Dual rate data transfers on both rising and falling edges of the clock. This technique doubles the amount of data transferred. Zero-Delay PLL clock drivers (buffer) and registers are required to meet the tight timing budget requirement of dual in-line memory modules (DIMM) & memory interface applications.
de-skew application: Platform’s with multiple FPGA’s or ASIC’s requires synchronous and phase aligned clocks. This can be achieved by de-skewing clock distribution network.
What’s on chip clock de-skewing? This is a requirement to phase align the output clock of a PLL to its input reference clock. In other words, remove the delay on the clock caused by noise and process variations on chip. For this applications we need Delay Locked Loop (DLL) type PLL’s. With use of DLL type devices, we can sample data synchronously without skewing and limiting the useful period of the clock.