# Verilog code and test-bench for logical shift left microoperations.

Related topics: ArithmeticLogicalShift micro-operations and digital Overflow with Verilog rtl discussion.
~\Documents\fullchip\python\mysite\webpages\templates\webpages\test.v.html
```// Test Bench for generating random numbers
module shift_tb ();
reg clk, rst;
reg[7:0] x_q;
reg[7:0] x_d;
reg[4:0] q_cnt;

integer k, i;
integer out;
// clock generation
initial
begin
clk = 0;
forever #10 clk = ~clk;
end
// reset release
initial begin
rst = 0;
# 50 rst = 1;
end
// Use positive edge of clock to shift the register value
// Implement logical left shift
always @(posedge clk or
negedge rst)
begin
if (!rst)
begin
x_q <= 'hed;
q_cnt <= 0;
out = \$fopen("shift_LL.vec","w");
end
else
begin
x_q <= x_d;
q_cnt <= q_cnt + 1;
\$fdisplay(out, "Pass %d Shift value in hex %b", q_cnt, x_q);
end
end
// shift logic
always @(*)
begin
x_d = x_q;
x_d[0] = 0;
for (i=0; i<8; i=i+1)
begin
x_d[i+1] = x_q[i];
end
end
endmodule
```

LTE - 4G Wireless Technology

Digital fundamentals.

Interview Questions.

Logical Shift Left micro-operation rtl code `simulation` results

Pass  0 Shift value in hex 11101101
Pass  1 Shift value in hex 11011010
Pass  2 Shift value in hex 10110100
Pass  3 Shift value in hex 01101000
Pass  4 Shift value in hex 11010000
Pass  5 Shift value in hex 10100000
Pass  6 Shift value in hex 01000000
Pass  7 Shift value in hex 10000000
Pass  8 Shift value in hex 00000000 <-- After shift 0 is filled in

Logical Shift Right (LSR) verilog code and simulation results. LSR discussion here.
Logical Shift left (LSL) verilog codesimulation results.
Circular Shift Right (CSR) verilog coderesults and discussion.
Circular Shift Left (CSL) verilog code, simulation results.
Related Topics: Arithmeticlogicalshift micro-operationsOverflow

Tutorials `@fullchipdesign.com`

Verilog Tutorial.

LTE Tutorial.

Memory Tutorial.

Hope you liked! this page. Don't forgot to access relevant `previous and next sections ` with links below.