Interrupts are generally implemented with a set of registers for each interrupt source.
Registers, VIC and NMI.
Registers required for implementing interrupt.
Interrupt status register (ISR) - Each bit of the register captures the status of the interrupts from individual peripherals.
Interrupt mask register (IMR) - Each bit of the register masks the interrupts from individual peripherals.
Interrupt pending register (IPR) - If IMR bit is set the interrupt will show-up in IPR bit.
Interrupt clear register (ICR) - Writing to this register bit will clear the intr bit from ISR.
Some essential features of interrupt controllers are below:
- Multiple interrupt request inputs gets stored in IPR and ISR. One bit is generally assigned for each interrupt source.
- Software can mask out particular interrupt requests by setting the corresponding bit in IMR.
- Interrupts can be prioritized in hardware by implementing interrupt nesting of hardware sources.
- Software is still expected to perform following functions in interrupt handler:
• Determine the interrupt source.
VIC Vectored Interrupt Controller
A Vectored Interrupt Controller (VIC) acts as a hardware accelerator for handling control for software and save the complexity and latency on software side. Both the hardware and software portions of Interrupt controller are handled within hardware block. This block supplies the start address and vector address of the service routines. This enables the highest priority request from the interrupt source.
Non-maskable Interrupt (NMI) -
An NMI can never be masked in hardware using IMR and are always propagated to the processor. Generally on getting a non-maskable interrupt the handler executes a piece of special monitor program. This monitor program manages the hardware failure scenario.