Verilog Initial Statements.
Initial statements with examples are discussed in this section. Also discussed are clocks and resets generation logic using forever loop and not operator.
Statements within initial block are used in Verilog for generating test signals, example clocks, resets etc.
Initial statements can’t be synthesized because actual behavior of hardware is difficult to model using fixed delays. These statements are used only for testbench purposes and to initialize the values at zero simulation time.
Clocks and reset generation in test-
Counter logic with enable disable logic generation using initial statements.