Formula to calculate FIFO depth below:
D = [B -
D = Depth or number of locations in FIFO to store.
B = Burst Width, number of words to store before idle time.
Clk_rd = Read side clock frequency.
Clk_wr = Write side clock frequency.
RD = Read side delay in-
Example to prove above formula below.
Example: Write side of FIFO:
Write clock frequency = 15 MHz (clk_wr)
Maximum size of the Burst = 100 bytes (burst_width)
Delay between writes in a burst = 1 clock cycle (wr_delay)
Read side of FIFO
Read clock Frequency = 10 MHz (clk_read)
Delay between reads = 2 clock cycles (rd_delay)
Apply formula to
calculate FIFO depth.
= 100 -
= 66.67 or 67
So we will need to design a FIFO 67 deep.