Conditional if-else construct in Verilog

Register transfer level (RTL) is used to create a high level description of a synchronous digital circuit.

If -else construct in RTL is used to generate priority logic. This construct prevents parallel processing in hardware.

If, else if and else constructs are used in both synchronous and combinational logic for priority generation.

~\Documents\fullchip\python\mysite\webpages\templates\webpages\test.v.html
 module ifcode (
            in_a,
            in_b,
            in_c,
            in_ctrl,
            out_d
    );
    // Define inputs/outputs
    input  in_a;
    input  in_b;
    input  in_c;
    input[1:0]  in_ctrl;
    output out_d;
    // Use of if statement. 
    always@(*)
    begin
      if (in_ctrl == 2'b00)
         out_d = in_a;
      else if (in_ctrl == 2'b01)
         out_d = in_b;
      else
         out_d = out_c;
    end
 end

LTE - 4G Wireless Technology

Digital fundamentals.

Interview Questions.

~\Documents\fullchip\python\mysite\webpages\templates\webpages\test.v.html
 module ifcode (
            in_a,
            in_b,
            in_c,
            in_ctrl,
            out_d
    );
    // Define inputs/outputs
    input  in_a;
    input  in_b;
    input  in_c;
    input[1:0]  in_ctrl;
    output out_d;
    // Use of if statement. 
    always@(*)
    begin
      if (in_ctrl == 2'b00)
         out_d = in_a;
      else if (in_ctrl == 2'b01)
         out_d = in_b;
      else
         out_d = out_c;
    end
 end

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Verilog Tutorial.

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