Conditional if- else construct in Verilog
Register transfer level (RTL) is used to create a high level description of a synchronous digital circuit.
If -
If, else if and else constructs are used in both synchronous and combinational logic for priority generation.
module ifcode ( in_a, in_b, in_c, in_ctrl, out_d ); // Define inputs/outputs input in_a; input in_b; input in_c; input[1:0] in_ctrl; output out_d; // Use of if statement. always@(*) begin if (in_ctrl == 2'b00) out_d = in_a; else if (in_ctrl == 2'b01) out_d = in_b; else out_d = out_c; end end