CMOS digital ASIC design process

CMOS is a Digital Integrated Circuit design process for Very large scale productions. The compact term for the process is CMOS VLSI (Very Large Scale Implementation).

This design flow is a custom flow targeted specifically for mass production of IC’s for various applications. The compact term for the flow is ASIC (Application specific Integrated circuits)

CMOS IC design Process

The CMOS circuit design process mainly involves following steps
1. Design Specifications.
2. Logic design, synthesis and timing analysis (with targeted layout libraries.) The final output of this process is a gate-level netlist. This step is also know as front-end design flow.
3. Translate gate level circuit into a layout primarily using CMOS cells.
4. Use the layout’s from step 3 to calculate initial performance parasitic’s using circuit extraction program’s.
5. Run simulations using parasitic's from step 4. Compare the results with step 1.
6. Optimize the circuit in step 3 using results from step 5 to achieve step 1.
7. Fabricate and test the circuit in step 3.

LTE - 4G Wireless Technology

Digital fundamentals.

Interview Questions.

CMOS Parasitics

A custom layout of any ASIC requires intensive knowledge of the parasitics involved.

Parasitics are listed below:-
1. Stray capacitances and leakage problems associated with it.
2. Mutual Inductances and problems with unwanted coupling between conductors.
3. Resistance's.
4. PN junctions.
5. Bipolar transistors.

Stay or parasitics capacitance’s are unwanted capacitance’s measured on the circuits which should ideally produce 0 F of capacitance. This effect occur’s over long periods.

Capacitance introduction:-
Lets first define the capacitance. Its the ability of two conductors to hold charge.
Otherwise, C = Q/V Farad
Where C is capacitance measured in Farad (F) unit. 1 F = 1 coulomb per volt
Q is charges on the conductors.
V is the voltage between conductors.

Some examples of parasitic capacitance sources are:-
1. Data or command bus lines to connect sub-systems on an SOC.
2. Address lines in memory arrays.

Performance limitations:-
This phenomenon can severely limit the current driving capability of CMOS gates.

This also increases the propagation delay and limits capacitive load carrying capacity.


Is the undesired interference on a conductor due to rate of change (with respect to time) of voltage on a parallel conductor.

Crosstalk can cause:-

1. Undesired Mutual Capacitance or Induced current.
2. Undesired Mutual Inductance or Induced voltage.

Crosstalk can be avoided by increasing the distance between the conductors.

Crosstalk as Induced current:-

The induced interference can be measured as current and can be represented with following equation.

I1 = Ctc * dV2/dt

Where:- I1 is undesired induced current, CtC is crosstalk mutual capacitance, V2 is voltage on the parallel conductor.

Crosstalk as Induced voltage:-

The induced interference can be measured as voltage and can be represented with following equation.

V1 = CtL * dI2/dt

Where:- V1 is undesired induced voltage, CtL is crosstalk mutual inductance, I2 is current on the parallel conductor.



Verilog Tutorial.

LTE Tutorial.

Memory Tutorial.

Ground Bounce causes and Prevention. 

Lets discuss ground bounce with the help of circuit below.

ground bounce in cmos

In the the circuit above the conductor 2 is connected to ground rail and expected voltage across the conductor is 0V. But in real circuits the conductor 2 itself has inductance. This inductance results in voltage (ground bounce) when current flows across the conductor. The unintended voltage or ground bounce can propagate to circuits and can cause issues.
Steps to reduce ground bounce in circuits.
1. Decrease the inductance of conductor 2.
2. Increase isolation capacitance. 

Hope you liked! this page. Don't forgot to access relevant previous and next sections with links below.