# Circular Shift Left micro-operation.

Verilog code for circular shift left microoperations.

~\Documents\fullchip\python\mysite\webpages\templates\webpages\test.v.html
```// Test Bench for generating random numbers
module shift_tb ();
reg clk, rst;
reg[7:0] x_q;
reg[7:0] x_d;
reg[4:0] q_cnt;

integer k, i;
integer out;
//clock
initial
begin
clk = 0;
forever #10 clk = ~clk;
end
//reset
initial begin
rst = 0;
# 50 rst = 1;
end
// Use positive edge of clock to shift the register value
// Implement cyclic shift left
always @(posedge clk or
negedge rst)
begin
if (!rst)
begin
x_q <= 'hed;
q_cnt <= 0;
out = \$fopen("shift_CL.vec","w");
end
else
begin
x_q <= x_d;
q_cnt <= q_cnt + 1;
\$fdisplay(out, "Pass %d Shift value in hex %b", q_cnt, x_q);
end
end
//shift logic
always @(*)
begin
x_d = x_q;
x_d[0] = x_q[7];
for (i=0; i<7; i=i+1)
begin
x_d[i+1] = x_q[i];
end
end
endmodule
```

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Circular Shift Left micro-operation rtl code simulation results

Pass 0 Shift value in hex 11101101
Pass 1 Shift value in hex 11011011
Pass 2 Shift value in hex 10110111
Pass 3 Shift value in hex 01101111
Pass 4 Shift value in hex 11011110
Pass 5 Shift value in hex 10111101
Pass 6 Shift value in hex 01111011
Pass 7 Shift value in hex 11110110
Pass 8 Shift value in hex 11101101 <-- Original binary value
Pass 9 Shift value in hex 11011011
Pass 10 Shift value in hex 10110111
Pass 11 Shift value in hex 01101111
Pass 12 Shift value in hex 11011110
Pass 13 Shift value in hex 10111101
Pass 14 Shift value in hex 01111011
Pass 15 Shift value in hex 11110110
Pass 16 Shift value in hex 11101101 <-- Original binary value

Logical Shift Right (LSR) verilog code and simulation results. LSR discussion here.
Logical Shift left (LSL) verilog codesimulation results.
Circular Shift Right (CSR) verilog coderesults and discussion.
Circular Shift Left (CSL) verilog code, simulation results.
Related Topics: Arithmeticlogicalshift micro-operationsOverflow

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