Discussion on various synthesis stages.

Synthesis steps from digital design from previous topic are discussed below.

Stage 1. Required inputs to EDA tool -  RTL, Technology library and synthesis constraints.

The input RTL, is the behavioural model of the functional specs of the hardware we want .

The input Technology library,  is a database of all technology elements like flops, fundamental gates and memories which are required to map behavioural rtl design into structural design.

The technology library has dedicated specifications in terms of operating voltage, area & operating conditions like temperature. Required wireload, in/out timings and logical symbols are also part of technology library.

In short its a database of all structural resources required to convert a RTL design into gate level netlist. Comprehensive details on structure of Synthesis Technology libraries are discussed here.

LTE - 4G Wireless Technology

Digital fundamentals.

Interview Questions.

The input constraints:

All digital design ASIC or FPGA’s consists of digital routes for signal propagation. These routes are mostly from flop-to-flop, input-to-flop or flop-to-output. The synthesis tools needs to understand the timing requirements for these routes. Also from flops we need to define clocks in the design. Other requirements to time in/out ports involve set_input_delay and set_output_delays. Many other requirements are part of digital synthesis constraints.

More detailed discussion on constraints is covered under this topic.

So rtl designers are required to provide these constraints.

Summary of this topic, we have discussed in some details the required inputs for synthesizing a digital design for ASIC/FPGA hardware implementations.

Next Synthesis stage (Stage2) is pre-processing of digital design using EDA tools.

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Tutorials @fullchipdesign.com

Verilog Tutorial.

LTE Tutorial.

Memory Tutorial.

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