Chip Designing for ASIC/ FPGA Design engineers and Students

FULLCHIPDESIGN

Digital-logic Design...  Dream for many students… start learning front-end…

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Topics @TYH :- 4G LTE Tutorial, GVIM editor, Smart-Phone, Cloud Computing

Computer Organization.
Memory Organization.
Cache Organization.
Interrupt controller.

XOR Truth Table:-

A B Y
0 0 0
0 1 1
1 0 1
1 1 0

XOR equation = A’B + AB’

NOR Truth Table

A B Y
0 0 1
0 1 0
1 0 0
1 1 0

NOR equation = A’ B’

Digital gate conversion interview questions.

NAND to Inverter. XOR from NAND and  XOR from NOR.

Lets start the discussion with truth tables of XOR and NOR gates.

Interview Questions. Main, FPGA, Digital basics  

check circuit for NOR to inverter (equivalent of NAND to inverter)
So the complete circuit for XOR using NOR gates is shown below.
Diagram shown below.

Arithmetic, logical and shift microoperations. Binary to Gray code conversion Readmemh, Readmemb. Random Memory Implementation - sync Ram and Testbench

Resources
Verilog RTL code examples for front-end chip design.
Digital Design Topics
Half-adder, full-adder,
Adder-sub tractor
Stack Organization - LIFO, RPN
Parity Generation and error checking
Binary multiplier circuit.
CMOS introduction
Digital fundamentals -
RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle
Pipeline vs. Parallel processing.

Universal NAND Gate.
Derive AND gate from NAND gate.
Derive OR gate from universal NAND gate.
Derive XOR gate from universal NAND gate.

Computer Organization Topics:
Computer Introduction.
Building blocks - ALU, ACC, Pc, Registers, Stack Pointer, IR, timing and control unit.
Memory Organization.

Assertions introduction, Concise assertions, Assertion levels

Digital Logic fundamentals topics @ fcd
Digital basics tutorial Binary number discussion, 1 and 2 complement discussion, Binary arithmetic, Signed Magnitude, overflow, examples. Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates Sum of Minterms, Product of Maxterms or Canonical Forms,
Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s.  Prime Implicant and Gate level minimization

Top Tech Topics @FCD
K-map - 2,3,4,5 var & Prime Implicant discussion
Verilog - learn with examples
Interview questions and hints

Hot Topics @FCD
Cloud Computing
Inside Smart Phones
Overflow
Binary adder-subtractor circuit
Full-adder RTL & test-bench

Misc. Verilog RTL examples:-
Binary to Gray Code conversion File read write operations.
Clock domain crossing. Half-adder, Full-adder, Tri-state buffer .Verilog testbench to validate half-adder, full-adder and tri-state buffer. VERILOG HOME

Half-Adder, Full-Adder, Adder-Subtractor.
Verilog code -
Half-Adder, Full-Adder

Arithmetic, logical, shift micro-operations, Overflow

K-map - 2,3,4,5 var & Prime Implicant discussion

Interview Questions. Main, FPGA, Digital Fundamentals

Return to Verilog Tutorial

Reformat XOR equation by following steps below:
Step 1 :- A'B + AB' +AA’ + BB’ = [(A’+B') (A+B)] using postulate P4 and theorems T7, T8 and T9

Step 2 :- [(AB)'(A’B’)’] using theorems T7, T8 and T9

In step 2, we do invert of A and invert of B.

Derive XOR only using NOR gates

4G LTE - Long Term Evolution topics from here