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Introduction Operators Initial stms Block vs. Non Blk IF-ELSE, CASE FORLOOP File Operations Read .bin format Function Call Testbench Random Numbers Shift Micro-ops Sync RAM Mem Generate Assertions
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Verilog Tutorial.
Computer Organization.
 Memory Organization.
 Cache Organization.
 Interrupt controller.
Digital Basics Tutorial.
~\Desktop\FCD\downloads\fc_v\memory_ram_sync_rtl.v.html module mem_ram_sync(
    clk,
    rst,
    read_rq,
    write_rq,
    rw_address,
    write_data,
    read_data
);
input           clk;
input           rst;
input           read_rq;
input           write_rq;
input[5:0]      rw_address;
input[7:0]      write_data;
output[7:0]     read_data;

reg[7:0]     read_data;

integer out, i;

// Declare memory 64x8 bits = 512 bits or 64 bytes
reg [7:0] memory_ram_d [63:0];
reg [7:0] memory_ram_q [63:0];

// Use positive edge of clock to read the memory
// Implement cyclic shift right
always @(posedge clk or
    negedge rst)
begin
    if (!rst)
    begin
        for (i=0;i<64; i=i+1)
            memory_ram_q[i] <= 0;
    end
    else
    begin
        for (i=0;i<64; i=i+1)
             memory_ram_q[i] <= memory_ram_d[i];
    end
end


always @(*)
begin
    for (i=0;i<64; i=i+1)
        memory_ram_d[i] = memory_ram_q[i];
    if (write_rq && !read_rq)
        memory_ram_d[rw_address] = write_data;
    if (!write_rq && read_rq)
        read_data = memory_ram_q[rw_address];
end
 
endmodule
In order to validate the memory implementation we will implement a model in verilog test-bench to generate the controls for the memory. The way we are going to model it is as follows.
First we are going to fill in the memory with write only commands. The data we are going to write will be random. After filling in the memory, we will enable reads. During reads we will request random addresses between 0 and 63. We will dump both read and write data in text files. Links to test-bench, write data/memory contents,
read data and analysis.
Memory Diagram, details
Misc. Verilog RTL examples:-

Binary to Gray Code conversion
 File read write operations.
 Clock domain crossing.
 Half-adder, Full-adder, Tri-state buffer .
 Verilog testbench to validate half-adder, full-adder and tri-state buffer.
VERILOG HOME
Verilog RTL code to implement synchronous RAM (Random Access Memory) and also provide a test-bench to validate it.
Synchronous Random Access Memory (RAM) implementation in verilog.
Digital Logic fundamentals topics @ fcd
Digital basics tutorial
 Binary number discussion, 1 and 2 complement discussion,
Binary arithmetic, Signed Magnitude, overflow, examples
Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates
 Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms
Sum of Minterms, Product of Maxterms or Canonical Forms,
Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s
 Prime Implicant and Gate level minimization examples.
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LTE Data rates and comparison with 3G rates.