Chip Designing for ASIC/ FPGA Design engineers and Students
Digital-logic Design... Dream for many students… start learning front-end…
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Introduction
Operators
Initial stms
Block vs. Non Blk
IF-ELSE, CASE
FORLOOP
File Operations
Read .bin format
Function Call
Testbench
Random Numbers
Shift Micro-ops
Sync RAM
Mem Generate
Assertions
Signed RTL
AND - True when all operands are TRUE
OR - True when any one operand is TRUE
Logical - Operation on registers as logical statements True and false. These are primarily used in conditional statements like ‘IF’, ‘ELSE IF’
True when arithmetic value of one register is greater than the other register in comparison.
True when arithmetic value of one register is less than the other register in comparison.
True when arithmetic value of one register is greater than or equal to the other register in comparison.
True when arithmetic value of one register is less than or equal to the other register.
‘==’ Logical equality excluding Tristate values (‘bX).
‘===’ Logical equality including Tristate values or ‘bX.
‘!=’ Logical in-equality excluding Tristate values or ‘bX.
‘!==’ Logical in-equality including Tristate values or ‘bX.
Shift - Shift values of registers and store the new value.
Shift the contents of register right and drop the bits.
Shift the contents of register left and drop the bits.
Supported Verilog 2001 onwards. Shift the contents of register right and store the bits in MSB bits.
Supported Verilog 2001 onwards. Shift the contents of register left and store the bits in lsb bits.
Binary Aritmetic Operators - Each bit of the register is individually operated with corresponding bit in other register.
Bitwise - Operation on individual bits of registers. Also discussed is the verilog code implementation.
Others - conditionals, concatenation and replicate.
Append two values in one register.
Example:- R3[5:0] = {R1[2:0],R2[2:0}
Where value of p is replicated r times
If condition is true, assign value V1 else V2.