Verilog operators, bitwise,Verilog binary arithmetic example, logical, shift, concatenation, replication, conditional. shift and store in register.

Home Verilog Digital Design Digital Basics Python RF Basics

Legal Disclaimer

Chip Designing for ASIC/ FPGA Design engineers and Students

FULLCHIPDESIGN

Digital-logic Design... Dream for many students… start learning front-end…

Topics @TYH :- 4G LTE Tutorial, GVIM editor, Smart-Phone, Cloud Computing

PICS

Custom Search

Feedback ? Send it to admin@fullchipdesign.com or join me at fullchip@gmail.com

Legal Disclaimer

FORUM

Introduction Operators Initial stms Block vs. Non Blk IF-ELSE, CASE FORLOOP File Operations Read .bin format Function Call Testbench Random Numbers Shift Micro-ops Sync RAM Mem Generate Assertions

FORUM

Computer Organization.
Memory Organization.
Cache Organization.
Interrupt controller.

Category

Name

Symbol

Details

Logical

AND

AND - True when all operands are TRUE

OR - True when any one operand is TRUE

NOT

Not is like a inverter.

Logical - Operation on registers as logical statements True and false. These are primarily used in conditional statements like ‘IF’, ‘ELSE IF’

Category

Name

Symbol

Details

Comparison

Greater than

True when arithmetic value of one register is greater than the other register in comparison.

Less than

True when arithmetic value of one register is less than the other register in comparison.

Greater than or equal

True when arithmetic value of one register is greater than or equal to the other register in comparison.

Greater than or equal

True when arithmetic value of one register is less than or equal to the other register.

Equal to

== or ===

‘==’ Logical equality excluding Tristate values (‘bX).
‘===’ Logical equality including Tristate values or ‘bX.

Not equal

!= or !==

‘!=’ Logical in-equality excluding Tristate values or ‘bX.
‘!==’ Logical in-equality including Tristate values or ‘bX.

Shift - Shift values of registers and store the new value.

Category

Name

Symbol

Details

Shift and store

Logical Right Shift

Shift the contents of register right and drop the bits.

Logical Left Shift

Shift the contents of register left and drop the bits.

Arithmetic Right Shift

>>>

Supported Verilog 2001 onwards. Shift the contents of register right and store the bits in MSB bits.

Arithmetic Left Shift

<<<

Supported Verilog 2001 onwards. Shift the contents of register left and store the bits in lsb bits.

Binary Aritmetic Operators - Each bit of the register is individually operated with corresponding bit in other register.

Category

Name

Symbol

Details

Bitwise - Refer verilog

Negation

1’s complement

Bitwise OR

Bitwise AND

Bitwise XOR

Bitwise - Operation on individual bits of registers. Also discussed is the verilog code implementation.

Category

Name

Symbol

Details

Bitwise , refer Verilog

Bitwise NAND

Bitwise NOR

Bitwise XNOR

Others - conditionals, concatenation and replicate.

Category

Name

Symbol

Details

Concatenation

{ , }

Append two values in one register.
Example:- R3[5:0] = {R1[2:0],R2[2:0}

Replication

{r{p}}

Where value of p is replicated r times

Conditional

(condition)? V1 : V2

If condition is true, assign value V1 else V2.

Previous Next

Did you like this page? Like us on Facebook

Chip Design <> Digital Basics <> 4G LTE <> Cloud Computing