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initial

begin

#0 X = 1; #0 Y = 2; #0 Z = 0;

#10 Z = X + Y;

end

begin

#0 X = 1; #0 Y = 2; #0 Z = 0;

#10 Z = X + Y;

end

initial

begin

#0 X = 1; #0 Y = 2; #0 Z = 0;

Z = #10 X + Y;

end

begin

#0 X = 1; #0 Y = 2; #0 Z = 0;

Z = #10 X + Y;

end

In the above example all three variables X, Y and Z will be initialized at time 0. The variable Z will get a sum of variables X and Y after delay of 10 time steps.

Behavioral modeling of hardware requires delay specifications. These delays are specified by using either inter statement or intra-statement delays. The details are discussed below with reference to Verilog/SystemVerilog test-benches.

Intra statements delay control: This is an alternate technique of delay modeling by inserting delay as a part of statement execution. Lets review the above example with intra-statement delays.

In the above example # delay is moved inside the statement after ‘=’ sign. This method of coding will cause the value of X+Y to be stored in a temporary register for 10 time units. After that delay (10 time units) the register Z will get updated. These are alternatively known as intra-assignments delay.

RTL Inter-statement and Intra-statement delay modeling

Inter-statement delay or normal delay control :- This is the most common approach of delay modeling in test-benches. In this technique a delay is inserted before or in-between statements . Above is an example of inter-statement delay.

Introduction to Verilog RTL

Verilog Operators.

Initial Statements in verilog.

Clock and Reset generation.

Blocking vs. Non-blocking Statements.

Conditional Statements & ‘always’ block.

Counter Implementation.

File Operations - $fopen, $fclose, $fdisplay, $fscanf

Read binary or hex files - $readmemh, $readmemb.

FOR Loop use in verilog code example

Verilog Operators.

Initial Statements in verilog.

Clock and Reset generation.

Blocking vs. Non-

Conditional Statements & ‘always’ block.

Counter Implementation.

File Operations -

Read binary or hex files -

FOR Loop use in verilog code example

Resources

Verilog RTL code examples for front-end chip design.

Digital Design Topics - Half-adder , full-adder , Adder-sub tractor

Stack Org LIFO, RPN

Parity Generation and error checking

Binary multiplier circuit.

CMOS introduction

Digital fundamentals -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle

Pipeline Parallel processing.

Verilog RTL code examples for front-

Parity Generation and error checking

Binary multiplier circuit.

CMOS introduction

Digital fundamentals -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle

Pipeline Parallel processing.

Interview Questions. Main, FPGA, Digital Basics

Return to Verilog Tutorial

Cloud Computing ?

Whenever a document or photo is uploaded on the web, a thread of cloud computing is active. Learn more from here.

Whenever a document or photo is uploaded on the web, a thread of cloud computing is active. Learn more from here.

Digital Logic fundamentals topics. Digital basics tutorial

Binary number discussion, 1 and 2 complement discussion,

Binary arithmetic, Signed Magnitude, overflow, examples

Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates

Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms

Sum of Minterms, Product of Maxterms or Canonical Forms,

Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s

Prime Implicant and Gate level minimization examples.

Binary number discussion, 1 and 2 complement discussion,

Binary arithmetic, Signed Magnitude, overflow, examples

Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates

Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra -

Karnaugh map or K-

Prime Implicant and Gate level minimization examples.

LTE - Long Term Evolution topics from here