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Register transfer level (RTL) is used to create a high level description of a synchronous digital circuit.
1. Conditional If -
Synchronous priority logic generation:-
Combinational logic generation :-
reg r_packet_in;
reg packet_in;
always@(posedge clk_1fs or negedge rst_n)
begin
if (!rst_n) begin
r_packet_in <= 'b0;
end
else begin
r_packet_in <= packet_in;
end
End
Check the complete implementation of the above logic in verilog testbench example.
Conditional statements and Counter code
2. Conditional Case Statements and counter code
Case statements are used in RTL design to model states in Finite State Machine and for generating conditional statements based on value of a particular register. Case statement implementation is shown below.
case (r_count)
10 : begin
packet_in = 'haa;
wr_en = 'b1;
end
11 : begin
packet_in = 'hbb;
wr_en = 'b1;
end
12 : begin
packet_in = 'hcc;
wr_en = 'b1;
end
13 : begin
packet_in = 'hdd;
wr_en = 'b1;
end
endcase
// Always block to Implement counters
always@(posedge clk_1fs or negedge rst_n)
begin
if (!rst_n) begin
r_packet_in <= 'b0;
r_count <= 'b0;
r_rd_count <= 'b0;
r_wr_en <= 'b0;
r_rd_en <= 'b0;
end
else begin
r_packet_in <= packet_in;
r_count <= count + 1 ;
r_rd_count <= rd_count + 1 ;
r_wr_en <= wr_en;
r_rd_en <= rd_en;
end end
Digital design resources
Clock Domain Crossing Discussion with
rtl & testbench example.
Rate change(asynchronous) FIFO design and fifo depth calculation.
Half-
VHDL rtl -
RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.
Digital design Interview questions.
FPGA Interview. FPGA flow.
Guide to Graduate studies in US
Pipeline vs. Parallel processing.
Digital basics tutorial
Binary number discussion, 1 and 2 complement discussion,
Binary arithmetic, Signed Magnitude, overflow, examples
Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates
Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra -
Karnaugh map or K-
Prime Implicant and Gate level minimization examples.
