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Verilog testbench to generate random numbers and use of $fdisplay to store it in a text file.

out = $fopen("rand.vec","w");

$fdisplay(out, "seed = %h, 1st random number in hexadecimal = 0x%h", seed, $random(seed));

$fdisplay(out, "seed = %h, 2nd random number in hexadecimal = 0x%h", seed, $random(seed));

$fdisplay(out, "seed = %h, 3rd random number in hexadecimal = 0x%h", seed, $random(seed));

$fdisplay(out, "seed = %h, 4th random number in hexadecimal = 0x%h", seed, $random(seed));

$fdisplay(out, "seed = %h, 5th random number in hexadecimal = 0x%h", seed, $random(seed));

Contents of the output text ‘rand.vec’ is displayed below.

seed = 23980634, 1st random number in hexadecimal = 0x12153524

seed = 92153206, 2nd random number in hexadecimal = 0xc0895e81

seed = 40895ccf, 3rd random number in hexadecimal = 0x8484d609

seed = 0484d4c4, 4th random number in hexadecimal = 0xb1f05663

seed = 31f054f5, 5th random number in hexadecimal = 0x06b97b0d

seed = 92153206, 2nd random number in hexadecimal = 0xc0895e81

seed = 40895ccf, 3rd random number in hexadecimal = 0x8484d609

seed = 0484d4c4, 4th random number in hexadecimal = 0xb1f05663

seed = 31f054f5, 5th random number in hexadecimal = 0x06b97b0d

Results are discussed below:-

Generating random numbers and $fdisplay in Verilog testbench.

Resources

Digital design resources

Clock Domain Crossing rtl & testbench.

Rate change (asynchronous) FIFO design and fifo depth calculation.

Half-adder , Full-adder , 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT, Arithmetic, logical, shift micro-operations . Stack organization, LIFO, RPN discussion.

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.

Digital design Interview questions.

FPGA Interview. FPGA flow.

Guide to Graduate studies in US

Pipeline vs. Parallel processing.

Digital design resources

Clock Domain Crossing rtl & testbench.

Rate change (asynchronous) FIFO design and fifo depth calculation.

Half-

Digital design Interview questions.

FPGA Interview. FPGA flow.

Guide to Graduate studies in US

Pipeline vs. Parallel processing.

Resources

Verilog RTL code examples for front-end chip design.

Digital Design Topics

Half-adder , full-adder ,

Adder-sub tractor

Stack Organization - LIFO, RPN

Parity Generation and error checking

Binary multiplier circuit.

CMOS introduction

Digital fundamentals -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle

Pipeline vs. Parallel processing.

Verilog RTL code examples for front-

Digital Design Topics

Half-

Adder-

Stack Organization -

Parity Generation and error checking

Binary multiplier circuit.

CMOS introduction

Digital fundamentals -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle

Pipeline vs. Parallel processing.

Arithmetic, logical and shift microoperations.

Binary to Gray code conversion

Readmemh, Readmemb. Random numbers

Memory Implementation - sync Ram and Testbench

Binary to Gray code conversion

Readmemh, Readmemb. Random numbers

Memory Implementation -

Digital Logic fundamentals topics @ fcd

Digital basics tutorial

Binary number discussion, 1 and 2 complement discussion,

Binary arithmetic, Signed Magnitude, overflow, examples

Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates

Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms

Sum of Minterms, Product of Maxterms or Canonical Forms,

Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s

Prime Implicant and Gate level minimization examples.

Digital basics tutorial

Binary number discussion, 1 and 2 complement discussion,

Binary arithmetic, Signed Magnitude, overflow, examples

Gray coding, Binary coded digital (BCD) coding, BCD addition

Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates

Discussion of Boolean Algebra with examples.

Duality Principle, Huntington Postulates, Theorems of Boolean Algebra -

Karnaugh map or K-

Prime Implicant and Gate level minimization examples.

Misc. Verilog RTL examples

Binary to Gray Code conversion

File read write operations.

Clock domain crossing.

Half-adder , Full-adder , Tri-state buffer .

Verilog testbench to validate half-adder , full-adder and tri-state buffer.

VERILOG HOME

Binary to Gray Code conversion

File read write operations.

Clock domain crossing.

Half-

Verilog testbench to validate half-

VERILOG HOME

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Enhanced Packet Data Gateway (ePDG)

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