LTE - 4G Wireless Technology

Digital fundamentals.

Interview Questions.

~\Documents\fullchip\python\mysite\webpages\templates\webpages\test.v.html
module tb ();
// reg and wire declarations
................................
always @(posedge clk or
   negedge rst)
begin
   if (!rst)
   begin
     q_cnt <= 0;
    write_data <= 'b0;
    out = $fopen("mem_ram.vec","w");
    rout = $fopen("mem_ram_read.vec","w");
   end
   else begin
       if (q_cnt < 63)  begin
           q_cnt <= q_cnt+1;
           write_data <= $random(seed) & 'hFF;
           read_rq <= 0;
           write_rq <= 1;
           rw_address <= q_cnt;
           $fdisplay(out, "Address::%d:: %b :: -- contents in hex %h", rw_address, write_data, write_data);
       end
       else begin
           q_cnt <= q_cnt;
           write_data <= write_data;
           rw_address <= $random(seed) & 'h3F;
           read_rq <= 1;
           write_rq <= 0;
           $fdisplay(rout,"Address::%d:: %b :: -- read contents in hex %h", rw_address, read_data, read_data);
end end end
................................
endmodule

Tutorials @fullchipdesign.com

Verilog Tutorial.

LTE Tutorial.

Memory Tutorial.

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