Chip Designing for ASIC/ FPGA Design engineers and Students
FULLCHIPDESIGN
Digital-logic Design... Dream for many students… start learning front-end…
Custom Search
Feedback ? Send it to admin@fullchipdesign.com or join me at fullchip@gmail.com
File Operations in verilog Test-Bench
External files are called in test-benches for reading in vectors and storing results of simulations for further analysis.
Most of the key operations involved in handling external files are discussed below with examples.
How to Open a file to read text.
read_file = $fopen(“readme.txt”, r);
The highlighted text in blue is used to show the command which will tell Verilog compiler to read the text file readme.txt.
Other similar option rb.
How to Open a file to read text.
read_file = $fopen(“readme.txt”, r);
The highlighted text in blue is used to show the command which will tell Verilog compiler to read the text file readme.txt.
Other similar option rb.
Example Verilog code to do file operations
always @(posedge clk or
negedge rst)
begin
if (!rst)
begin
q_cnt <= 0;
write_data <= 'b0;
out = $fopen("mem_ram.vec","w");
rout = $fopen("mem_ram_read.vec","w");
end
else begin
if (q_cnt < 63) begin
q_cnt <= q_cnt+1;
write_data <= $random(seed) & 'hFF;
read_rq <= 0;
write_rq <= 1;
rw_address <= q_cnt;
$fdisplay(out, "Address::%d:: %b :: -- contents in hex %h", rw_address, write_data, write_data);
end
else begin
q_cnt <= q_cnt;
write_data <= write_data;
rw_address <= $random(seed) & 'h3F;
read_rq <= 1;
write_rq <= 0;
$fdisplay(rout,"Address::%d:: %b :: -- read contents in hex %h", rw_address, read_data, read_data);
end end end
always @(posedge clk or
negedge rst)
begin
if (!rst)
begin
q_cnt <= 0;
write_data <= 'b0;
out = $fopen("mem_ram.vec","w");
rout = $fopen("mem_ram_read.vec","w");
end
else begin
if (q_cnt < 63) begin
q_cnt <= q_cnt+1;
write_data <= $random(seed) & 'hFF;
read_rq <= 0;
write_rq <= 1;
rw_address <= q_cnt;
$fdisplay(out, "Address::%d:: %b :: -
else begin
q_cnt <= q_cnt;
write_data <= write_data;
rw_address <= $random(seed) & 'h3F;
read_rq <= 1;
write_rq <= 0;
$fdisplay(rout,"Address::%d:: %b :: -
end end end
How to Open a file to write text.
write_file = $fopen(“readme.txt”, w);
The highlighted text in blue is used to show the command which will tell Verilog compiler to write to the text file readme.txt after erasing all the data from it.
Other similar option wb.
How to Open a file to append text.
append_file = $fopen(“readme.txt”, a);
The highlighted text in blue is used to show the command which will tell Verilog compiler to open the text file readme.txt and append more text at the end of the file.
Other similar option ab.
write_file = $fopen(“readme.txt”, w);
The highlighted text in blue is used to show the command which will tell Verilog compiler to write to the text file readme.txt after erasing all the data from it.
Other similar option wb.
How to Open a file to append text.
append_file = $fopen(“readme.txt”, a);
The highlighted text in blue is used to show the command which will tell Verilog compiler to open the text file readme.txt and append more text at the end of the file.
Other similar option ab.
$fopen, $fclose, $fdisplay, $fscanf are discussed on this page with examples
Arithmetic, logical and shift microoperations.
Binary to Gray code conversion
Readmemh, Readmemb. Random numbers
Memory Implementation - sync Ram and Testbench
Binary to Gray code conversion
Readmemh, Readmemb. Random numbers
Memory Implementation -
Resources
Verilog RTL code examples for front-end chip design.
Digital Design Topics
Half-adder , full-adder ,
Adder-sub tractor
Stack Organization - LIFO, RPN
Parity Generation and error checking
Binary multiplier circuit.
CMOS introduction
Digital fundamentals -
RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle
Pipeline vs. Parallel processing.
Verilog RTL code examples for front-
Digital Design Topics
Half-
Adder-
Stack Organization -
Parity Generation and error checking
Binary multiplier circuit.
CMOS introduction
Digital fundamentals -
RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle
Pipeline vs. Parallel processing.
Interview Questions. Main, FPGA, Digital Fundamentals
LTE - Long Term Evolution topics from here
Previous Next
Reading text in specified format from opened file. ( Supported in Verilog-2001)
Read the data in specified format (hexadecimal, binary or octal) and store it in a register.
read_data = $fscanf(read_file, “%format”, register_to_store_data);
Read the data in specified format (hexadecimal, binary or octal) and store it in a register.
read_data = $fscanf(read_file, “%format”, register_to_store_data);
How to Open a file to both read and write text.
rw_file = $fopen(“readme.txt”, r+);
The highlighted text in blue is used to show the command which will tell Verilog compiler to open the text file readme.txt to enable both reads and writes to it.
Other similar option r+b or rb+.
How to Close or release an open file.
$fclose(readme.txt);
Writing text into the opened file.
Write to file starting at a new line.
$fdisplay(write_file, “comments”, write_data);
rw_file = $fopen(“readme.txt”, r+);
The highlighted text in blue is used to show the command which will tell Verilog compiler to open the text file readme.txt to enable both reads and writes to it.
Other similar option r+b or rb+.
How to Close or release an open file.
$fclose(readme.txt);
Writing text into the opened file.
Write to file starting at a new line.
$fdisplay(write_file, “comments”, write_data);
Cloud Computing ?
Whenever a document or photo is uploaded on the web, a thread of cloud computing is active. Learn more from here.
Whenever a document or photo is uploaded on the web, a thread of cloud computing is active. Learn more from here.
Interview Questions. Main, FPGA, Digital Fundamentals