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Verilog in a day ? may be .. online and easy access with many examples.
verilog_tutorial.htm

FPGA build flow.
fpga_synthesis_pinmap_constraints_sta.htm

4G LTE differences in FDD and TDD modes.
lte_fdd_tdd_frame_modes_synchronization.htm

LTE access technologies in FDD and TDD modes for transmit and receive.
lte_fdd_tdd_scfdma_ofdma.htm

Verilog Blocking & Non-blocking statements.
blocking_non-blocking_statements.htm

How to check error in digital transmit and receive communication... use Parity Generation and Checking ...
parity_generation_checking.htm

FIFO in digital design .. how to determine FIFO depth.
fifodepth.htm

Verilog online tutorial with many examples.
verilog_tutorial.htm

Selecting a correct PLL earlier in design of ASIC, FPGA or SOC is critical.
pll_asic_chip_digital.htm

Differentiate with new skills in your resume .. but never forget fundamentals
digitalbasicstut.htm

Shift micro-operations in Verilog RTL?
verilog_logical_shift_right_microoperation.htm

Verilog RTL code for synchronization logic to implement clock domain crossing circuit.

Setup, Hold time & meta-stability of flop.

RTL - Register Transfer Level for modeling digital hardware.

FOR loops on hardware .. Recommended?