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Fullchipdesign.com - Topics covered in Verilog RTL, Digital Design, Digital Basics, Radio Frequency and Python Scripting.  

S5 - Interface between Serving GW and PDN GW.
Functionality
1. User plane tunneling and tunnel management.
2. It is used for Serving GW relocation due to UE mobility or connections to a non-collocated PDN GW.

S6a - Interface between HSS and MME
Functionality
1. Enables transfer of subscription and authentication data. Required for evolved system - AAA interface.

S8 - Interface between
Serving GW in the VPLMN and the PDN GW in the HPLMN.
Functionality
Inter-PLMN reference point providing user and control plane between the Serving GW in the VPLMN and the PDN GW in the HPLMN.

UMTS LTE Interfaces - Part 2

Evolved Packet Core (EPC) system architecture for all IP.Mobility Management Entity (MME),
Serving System (S) Architecture (A) Evolution (E) Gateway or Serving Gateway SGW.
Packet Data Network (PDN) SAE Gateway
Enhanced Packet Data Gateway (ePDG)
Multiple antenna techniques -
MIMO, Adaptive antenna systems - AAS and
Antenna diversity - AD

LTE topics @ FCD

What is LTE? Key driving factors behind 4G technology.
LTE Data rates and comparison with 3G rates.
Difference between air, radio and core network..  
Seamless mobility in 4G.

Resources @ fullchipdesign.com
Verilog RTL code examples for front-end chip design.
Digital Design Topics
Half-adder, full-adder,
Adder-sub tractor
Stack Organization - LIFO, RPN
Parity Generation and error checking
Binary multiplier circuit.
CMOS introduction
Digital fundamentals -
RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle
Pipeline vs. Parallel processing.

Hardware components of a smart-phone.
CPU or processor of a cell phone.,
Operating System or simply O/S
RAM, a type of memory and SD Memory
Applications for direct user interface.
PIXELS for resolution of screen.

Cloud Computing - another Internet revolution ?

Part1 Part2 Part3

LTE Interfaces Part1 Part2 Part3

LTE cells, network. UMTS LTE cell search, cell identities and synchronization signals (primary and secondary).  
2X2 MIMO, DL MIMO frame format 2x2, UL MIMO frame format 2x2.
4G LTE differences in FDD and TDD modes.

Computer Organization Topics:
Computer Introduction.
Building blocks - ALU, ACC, Pc, Registers, Stack Pointer, IR, timing and control unit.
Memory Organization.

Universal NAND Gate.
Derive AND gate from NAND gate.
Derive OR gate from universal NAND gate
Derive XOR gate from universal NAND gate.

Assertions introduction
Concise assertions
Assertion levels

GVIM Advance - regular expressions

Media Gallery
Las Vegas Grand Canyon Alcatraz -the rock
San Francisco Napa Valley Los Angeles
17 Mile Drive Golden Gate Bridge
Blog- Planning California Trip

Verilog RTL code examples for front-end chip design

Interview Questions. Main, FPGA, Digital Fundamentals

Arithmetic, logical and shift microoperations.
Binary to Gray code conversion
Readmemh, Readmemb. Random numbers
Memory Implementation - sync Ram and