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Memory sub-system, IO control & Bus sub-system.  

The memory unit is a critical component of digital computing where data needs to be read, processed and stored frequently.  Following block diagram shows the connectivity of CPU, memory and I/O unit through bus connections.  As the requirements of storage capacity increases with the processing power of CPU, we need to design systems with several levels of storage. This levels of hierarchy requires several tradeoffs on design platform.  One such tradeoff is with distance of the memory from CPU. As the distance increases, the delay on data transfer increases which in-turn reduces overall performance of the device reduces.

We have already covered CPU in previous section. Lets discuss the memory sub-system here.

Resources

Verilog RTL code examples for front-end chip design.

Digital Design Topics
Half-adder, full-adder,
Adder-sub tractor
Stack Organization - LIFO, RPN
Parity Generation and error checking
Binary multiplier circuit.
CMOS introduction
Digital fundamentals -
RTL coding guidelines. ICG cell, Assertions, $assertkill, levels. Chandle
Pipeline vs. Parallel processing.

Introduction to Verilog RTL
Verilog Operators.
Initial Statements in verilog.
Clock and Reset generation.
Blocking vs. Non-blocking Statements.
Conditional Statements & ‘always’ block.
Counter Implementation. File Operations - $fopen, $fclose, $fdisplay, $fscanf. Read binary or hex format files - $readmemh, $readmemb. FOR Loop use in verilog code example

Function declaration and call.
Testbench structure.
Random number generation.
Shift micro-operations use in rtl.
Memory - synchronous RAM implementation.
Verilog generate for memory instances.
Assertions in Verilog Introduction and few examples.

Arithmetic, logical and shift microoperations.
Binary to Gray code conversion
Readmemh, Readmemb. Random numbers
Memory Implementation - sync Ram and Testbench

Digital Logic fundamentals topics @ fcd Digital basics tutorial
Binary number discussion, 1 and 2 complement discussion, Binary arithmetic, Signed Magnitude, overflow, examples Gray coding, Binary coded digital (BCD) coding, BCD addition Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates Discussion of Boolean Algebra with examples. Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms . Sum of Minterms, Product of Maxterms or Canonical Forms, Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s Prime Implicant and Gate level minimization examples.

Computer memories are divided into Cache memory, main memory and secondary memory. Where Cache is the fastest and closest to processor. Cache memory is also the smallest memory. Secondary memory is the slowest, furthest from processor and largest in size.

Universal NAND Gate.
Derive AND gate from NAND gate.
Derive OR gate from universal NAND gate
Derive XOR gate from universal NAND gate.

Assertions introduction
Concise assertions
Assertion levels

Computer Organization Topics:
Computer Introduction.
Building blocks - ALU, ACC, Pc, Registers, Stack Pointer, IR, timing and control unit.
Memory Organization.

K-map - 2,3,4,5 var & Prime Implicant discussion

Arithmetic, logical, shift micro-operations, Overflow

Interview Questions. Main, FPGA, Digital Fundamentals

LTE - Long Term Evolution topics.

CPU

Memory

I/O Bus sub-system

Memory Bus sub-system

Block diagram on right shows the connectivity of CPU, memory and I/O unit through bus connections. Memory needs to be organized around CPU and central bus-sub system. Central bus-subsystem is also know as memory bus-subsystem and needs to handle all data  communication in-between cpu and main memory.    

Computer Organization Topics:
Computer Introduction.
Building blocks - ALU, ACC, Pc, Registers, Stack Pointer, IR, timing and control unit.
Memory Organization.