An easy approach to understand tech specs

Learn to Impress

Fullchipdesign.com - Topics covered in Verilog RTL, Digital Design, Digital Basics, Radio Frequency and Python Scripting.  

ePDG

IP Networks

SGSN

Operator’s IP
Services (IMS, PSS etc.)

SGW is shown in diagram below.

Some of the key roles of SGW are listed below:-

SGW is responsible for handovers with neighboring eNodeB’s.

Data transfer in terms of all packets across user plane.

Mobility interface (or anchors) to other 3GPP systems (2G and 3G) etc.

Serving (S) System Architecture Evolution Gateway  (GW)- SGW

SGW also monitors and maintains context information related to the UE during idle state and generates paging requests when data for the UE arrives from the network (on Downlink).

SGW also performs replication of the user traffic in case of lawful interception.

SGW

Evolved Packet Core (EPC) system architecture for all IP.Mobility Management Entity (MME),
Serving System (S) Architecture (A) Evolution (E) Gateway or Serving Gateway SGW.
Packet Data Network (PDN) SAE Gateway
Enhanced Packet Data Gateway (ePDG)
Multiple antenna techniques - MIMO, Adaptive antenna systems - AAS and Antenna diversity - AD

LTE topics @ FCD

What is LTE? Key driving factors behind 4G technology.
LTE Data rates and comparison with 3G rates.
Difference between air, radio and core network..  
Seamless mobility in 4G.

LTE cells, network. LTE cell search, cell identities & sync signals (primary and secondary).  2X2 MIMO, DL MIMO frame format 2x2, UL MIMO frame format 2x2. 4G LTE differences in FDD and TDD modes.
UMTS LTE Reference Signals. DMRS pilot demodulation

Media Gallery

Las Vegas
Grand Canyon
Alcatraz -the rock
San Francisco
Napa Valley
Los Angeles
17 Mile Drive
Golden Gate Bridge
Blog- Planning California Trip

Hardware components of a smart-phone.
CPU or processor of a cell phone.
Operating System or simply O/S
RAM, a type of memory and SD Memory
Applications for direct user interface.
PIXELS for resolution of screen.

Computer Organization Topics:
Computer Introduction.
Building blocks - ALU, ACC, Pc, Registers, Stack Pointer, IR, timing and control unit.
Memory Organization.