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Interrupt Controller Discussion.
Interrupt controller
An interrupt controller is an on chip device to manage interrupts from various different  peripheral  devices. These devices are generally connected through a bus sub-system driven by processor or in some cases Bus Master’s on chip.
Interrupt
An Interrupt is a request to processor to serve routines from peripherals in an out-of-turn basics.
Vectored Interrupt controller mechanism is discussed in details below. Lets start with a detailed block diagram of VIC (Vectored Interrupt Controller).
Software subroutines which manages the execution of a program
in response to an interrupt are commonly know as interrupt handlers or Interrupt Service Routines (ISR).

Interrupts are generally implemented with a set of registers for each interrupt source.
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Interrupt controllers are widely used in industry for processor based design. The VIC approach is specific to a design where each interrupt gets a dedicated vector list. This technique eliminates source polling and widely known as Vectored Interrupt control scheme.

Following blocks from the above diagram are further discussed on this site.

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