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Direct mapped cache memory complete hardware circuit.
This technique of placing a group of main memory locations into  a fixed cache line is termed as Direct-mapped Cache.

We have discussed the direct-mapped cache in previous topic. The details on Cache line, TAG memory and various control flags  can also be referred from previous topics. To implement an efficient control circuit in hardware requires following approach.  
Interview Questions.
Main, FPGA, Digital Fundamentals
Direct-Mapped Cache Memory complete hardware block diagram below.
Block Nos (TAG)
Group
No of Bytes (offset)
Any 1 of 32 TAGs = (2^5)
Any 1 of 256 groups (2^8)
Any 1 of 8 bytes = (2^3)
Cache line 0 (upto8 bytes)
Cache line 1
Cache line 2
....
....
Cache line P
MULTIPLEXER
8 to 256 de-mux
Comparator
Data to Processor
Match = Cache Hit
NO-Match = Cache Miss
AND
Block Nos (TAG)
Group
No of Bytes (offset)
Any 1 of 32 TAGs = (2^5)
Any 1 of 256 groups (2^8)
Any 1 of 8 bytes = (2^3)
For direct mapped cache memory we will need to partition address into following fields.