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Home Memory Dis Cache Memory Associative Cache Cache Hardware Cache control ACache arch Memory Array Direct Mapped Cache Direct Mapped D
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Direct mapped cache memory detailed discussion.
Interview Questions.
Main, FPGA, Digital Fundamentals
Direct-Mapped Cache Memory complete hardware block diagram
Block Nos (TAG)
Group
No of Bytes (offset)
Any 1 of 32 TAGs = (2^5)
Any 1 of 256 groups (2^8)
Any 1 of 8 bytes = (2^3)
Cache line 0 (upto8 bytes)
Cache line 1
Cache line 2
....
....
Cache line P
GP0
GP1
GP2
....
....
GP255
MULTIPLEXER
8 to 256 de-mux
Comparator
Data to Processor
Match = Cache Hit
NO-Match = Cache Miss
AND
Detailed Discussion.

A number of groups from main memory array is loaded into the GRP memory. GRP memory acts as storage of group numbers. When processor looks for an address to be read its divided into 3 fields. The fields are tag, group and byte.  First field which gets decoded is group number, its then matched with content of GRP memory of cache. Once the group is matched with a particular GRP memory  location then second level of decode happens.  The second level of decode involves matching of tag field of address to match with content of matched GRP location. The GRP location can only contain one TAG. If the Tag of GRP memory matches the TAG field of address its a CACHE HIT else CACHE MISS.

With CACHE hit third level of decode happens. In this step the corresponding cache line is read out and a particular byte is selected from it to match the byte field of address. The output of final step is shown above at output of multiplexor. The value is then sent out as read response to processor.