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Home Memory Dis Cache Memory Associative Cache Cache Hardware Cache control ACache arch Memory Array Direct Mapped Cache Direct Mapped D
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For direct mapped cache memory we will need to partition address into following fields.  
Direct mapped cache memory complete hardware circuit.
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Main, FPGA, Digital Fundamentals
In order to understand direct-mapped cache we will need to first partition main memory into an array where rows are called GROUP’s and columns are called TAG’s.  Then we can place each group into a fixed cache line. This technique of placing a group of main memory locations into  a fixed cache line is termed as Direct-mapped Cache.
With above partition we can implement a direct-mapped cache. Here we will have a fixed match of the cell from the array of main memory into a Cache tag location. Each TAG location need to match the group number in the address field. Next the content in tag memory needs to match the TAG ID. Once a match on TAG ID the data can then be fetched from the corresponding cache line.
The partition of main memory for direct mapped cache implementation is discussed below
0
256
..
..
..
(255*31)+1
1
257
..
..
..
255
511
2^13 -1
Main Memory structure for Direct- mapped CACHE
Groups (0 to 255)
TAGS (0 to 31)
Block Nos (TAG)
Group
No of Bytes (offset)
Any 1 of 32 TAGs = (2^5)
Any 1 of 256 groups (2^8)
Any 1 of 8 bytes = (2^3)
Complete hardware architecture of direct-mapped cache is discussed in next topic.
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