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Fully- Associative Cache Memory.
Fully Associative Cache Memory: This cache is most flexible cache architecture where data blocks from main memory can be paced in any location in cache memory.  In other words, this cache has ‘P’ locations to store data from Main Memory. The value of ‘P’ is always less than ‘N’ which represents total number of blocks present in main memory.
In above example/diagram the address width for main memory is 16 bits. The 16 bits are spit into two groups. The first group is called TAG of 13 bits and second group is OFFSET of 3 bits deep.
LTE - Long Term
Block 0
Block 1
Block 2
....
....
Block N
Address (8 locations in 1 block.)
0x0000
0x0001
0x0002
0x0003
0x0004
0x0005
0x0006
0x0007
Block Nos (TAG)
No of Bytes (offset)
Any 1 of 8192 = (2^13)
Any 1 of 8 = (2^3)
Implementation of cache requires a separate set of locations for storing the memory content and address of data blocks. The set of locations which store the main memory content are called cache lines. The locations which store upper TAG bits are called TAG memory.  So if cache line 0 has block 7 from main memory then Tag memory will have value 0x0007.  
Another set of 1 bit location are kept aside for storing a valid flag for data in cache memory.

NEXT Topic: Block diagram for cache memory.  
Implementation of Fully Associative Cache:
Interview Questions. Main, FPGA, Digital Fundamentals
Main Memory structure (NX8 bytes total)