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Verilog Tutorial.
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Computer Organization.
 Memory Organization.
 Cache Organization.
 Interrupt controller.
Digital Basics Tutorial.

Example:- Signed Magnitude Arithmetic

Final Answer. The arithmetic sum of two numbers +25 and -37 using signed magnitude method is -12 (10001100)  

Store Sign as MSB Bit = 1

Example 1: Add -37 to +25 using 2’s complement & signed magnitude

2’s complement of remaining bits as result = 0001100

Binary Numbers 1s_complement 2s_complement Binary Subtraction Binary Sub. Ex's Sign_magnitude SignM EX Gray Coding BCD coding Digital gates NAND NOR & XNOR Theorems Boolean Functions BFunc Examples Minterm Maxterm Sum of Minterms Prdt of Maxterms 2 var K-map 3 var K-map 4 var K-map 5 var K-map Prime Implicant PI example K-map Ex's KMap minimization
Digital Logic fundamentals topics @ fcd
Digital basics tutorial
 Binary number discussion, 1 and 2 complement discussion,
Binary arithmetic, Signed Magnitude, overflow, examples
Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR). Drive XOR from NAND gates. Drive XOR from NOR gates
 Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples, Boolean Functions, Canonical and Standard Forms, Minterms and Maxterms
Sum of Minterms, Product of Maxterms or Canonical Forms,
Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s
 Prime Implicant and Gate level minimization examples.
Introduction to Verilog RTL
 Verilog Operators.
 Initial Statements in verilog.
 Clock and Reset generation.
Blocking vs. Non-blocking Statements.
 Conditional Statements & ‘always’ block.
 Counter Implementation.
 File Operations - $fopen, $fclose, $fdisplay, $fscanf
 Read binary or hex format files - $readmemh, $readmemb.
Function declaration and call.
 Testbench structure.
 Random number generation.
 Shift micro-operations use in rtl.
 Memory - synchronous RAM implementation.
 Verilog generate for memory instances.
 Assertions in Verilog Introduction and few examples.
Verilog Tutorial Topics @ fullchipdesign.
Resources

Digital Design Topics
 Half-adder, full-adder,
 Adder-sub tractor
 Stack Organization - LIFO, RPN
 Parity Generation and error checking
 Binary multiplier circuit.
CMOS introduction
 Digital fundamentals -
RTL coding guidelines. ICG cell, Assertions, levels. Chandle
 Pipeline vs. Parallel processing.
Overflow conditions and examples.
Arithmetic, logical, shift micro-ops, Overflow
K-map - 2,3,4,5 var & Prime Implicant discussion
+25
In signed convention
00011001
-37
In 2’s complement
11011011
Equivalent result
11110100
Interview Questions. Main, FPGA, Digital Fundamentals
LTE - Long Term Evolution topics from here
Access Signed magnitude and 2’s complement topics
Access Signed magnitude and 2’s complement topics