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Verilog RTL.
Verilog is a programming language specifically designed to program hardware at Register Transfer Level (RTL). Follow the link to Verilog examples home page:
‘IF-ELSE’ , ‘case’ statement and synchronous counters
$Readmemh code to read hex values, function Declaration,
File read write ‘readmemh’ in verilog test-bench (tb)
Verilog code for Clock Domain Crossing.
Verilog testbench example for clock domain crossing.
Binary to Gray code conversion code.
Half-adder, Full-adder , Tri-state buffer and tb
Digital counter enable/disable logic in rtl and tb
$Readmemh code to read hex values, function Declaration,
File read write ‘readmemh’ in verilog test-
Verilog code for Clock Domain Crossing.
Verilog testbench example for clock domain crossing.
Binary to Gray code conversion code.
Half-
Digital counter enable/disable logic in rtl and tb
Resources
Digital design resources
Clock Domain Crossing Discussion with
rtl & testbench example.
Rate change(asynchronous) FIFO design and fifo depth calculation.
Half-adder & Full-adder circuit discussion with rtl & testbench
VHDL rtl - Synchronous flip-flop , latch, shim to improve timing and counter example
RTL coding guidelines for ASIC/FPGA.
Digital design Interview questions.
Guide to Graduate studies in US
rtl & testbench example.
Rate change(asynchronous) FIFO design and fifo depth calculation.
Half-
VHDL rtl -
RTL coding guidelines for ASIC/FPGA.
Digital design Interview questions.
Guide to Graduate studies in US
Try navigation bar on top to explore the contents @ fullchipdesign
RF basics.
RF fundamentals discussion
Signal to Noise ratio (SNR), NoiseFactor(F), NoiseFigure(NF)
Dynamic Range (DR), Minimum Detectable Signal (MDS),
Intermodulation (IM) distortion, Second order (IP2)
Third order (IP3) intermodulation products, IP3 (Third Order Intercept) plot,
Desensitization, Cross-modulation, Spurious outputs, Gain control, Noise
RF fundamentals discussion
Signal to Noise ratio (SNR), NoiseFactor(F), NoiseFigure(NF)
Dynamic Range (DR), Minimum Detectable Signal (MDS),
Intermodulation (IM) distortion, Second order (IP2)
Third order (IP3) intermodulation products, IP3 (Third Order Intercept) plot,
Desensitization, Cross-
Digital Logic fundamentals -
Digital basics tutorial
Binary number discussion, 1 and 2 complement discussion,
Binary arithmetic, Signed Magnitude discussion with examples,
Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR).
Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra - discussion with examples,
Boolean Functions,
Canonical and Standard Forms, Minterms and Maxterms
Sum of Minterms, Product of Maxterms or Canonical Forms,
Karnaugh map or K-map discussion 2, 3, ,4 and 5 var’s
Prime Implicant and Gate level minimization examples.
Digital basics tutorial
Binary number discussion, 1 and 2 complement discussion,
Binary arithmetic, Signed Magnitude discussion with examples,
Gray coding, Binary coded digital (BCD) coding, BCD addition
Digital logic gates basic (AND, OR, XOR, NOT) and derived (NAND, NOR and XNOR).
Discussion of Boolean Algebra with examples.
Duality Principle, Huntington Postulates, Theorems of Boolean Algebra -
Boolean Functions,
Canonical and Standard Forms, Minterms and Maxterms
Sum of Minterms, Product of Maxterms or Canonical Forms,
Karnaugh map or K-
Prime Implicant and Gate level minimization examples.
