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Product of Maxterms can be simply obtained by taking the complement of sum of Minterms from the Truth Table.

Example: Represent F = x + yz + xy in Product of Sum terms

F = (x + yz + x)(x + yz + y)

= (x + yz)(x + y +yz)

= (x + y)(x +z)(x + y + y)(x + y + z)

= (x +y)(x + z)(x + y)(x + y + z)

= (x +y + zz’)(x + z + yy’)(x +y +z)

= (x + y + z)(x +y + z’)(x + z + y)(x + z + y’)(x + y + z)

= (x + y + z)(x + y + z’)(x + y’ +z)

Answer.

Representation of Boolean Function in Product of Maxterms or Canonical Forms

x

y

z

Minterm in Function

Maxterm in Function

= (Minterm in Function)’

= (Minterm in Function)’

Maxterms

0

0

0

0

1

x + y+ z

0

0

1

1

0

0

1

0

1

0

0

1

1

0

1

x + y’ + z’

1

0

0

0

1

x’ + y + z

1

0

1

1

0

1

1

0

1

0

1

1

1

1

0

F1 = (x + y + z)( x + y’ + z’ )( x’ + y + z)

Product of Sum terms function F1 is

Resources

Digital design resources

Clock Domain Crossing Discussion with

rtl & testbench example.

Rate change(asynchronous) FIFO design and fifo depth calculation.

Half-adder , Full-adder , 4-bit binary adder , adder-subtractor circuit, overflow with rtl & testbench. Binary Multiplier, Parity error TT

Arithmetic, logical, shift micro-operations . Stack organization, LIFO, RPN discussion.

VHDL rtl - Synchronous flip-flop , latch, shim to improve timing and counter example

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.

Digital design Interview questions.

FPGA Interview. FPGA flow.

Guide to Graduate studies in US

Pipeline vs. Parallel processing.

Digital design resources

Clock Domain Crossing Discussion with

rtl & testbench example.

Rate change(asynchronous) FIFO design and fifo depth calculation.

Half-

VHDL rtl -

RTL coding guidelines. ICG cell, Assertions, $assertkill, levels.

Digital design Interview questions.

FPGA Interview. FPGA flow.

Guide to Graduate studies in US

Pipeline vs. Parallel processing.