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ASIC and FPGA: PLL applications

Selecting a correct PLL earlier in design of ASIC, FPGA or SOC is critical.
ASIC clock generation: Generation of high frequency clocks from low frequency reference.

DDR (double data rate): Dual rate data transfers on both rising and falling edges of the clock. This technique doubles the amount of data transferred. Zero-Delay PLL clock drivers (buffer) and registers are required to meet the tight timing budget requirement of dual in-line memory modules (DIMM) & memory interface applications.
Multiple clock options from PLL’s on ASIC’s/ FPGA’s
High speed clock multiplication and various frequency options. An important requirement to run various interfaces on chip at different frequencies. Here are some important blocks on chip: DDR, AXI buses, DMA’s, modems, rate change FIFO’s.

Requirements like minimum period jitter, low tracking jitter, low long-term jitter are achieved by using PLL’s.

Rejection of ISI (Inter Symbol Interference), which is an important requirement for RF SERDES interfaces is also met using PLL’s.
2) Software options to generate multiple divided phase aligned outputs. Like divided by 2, 4, 8 to clock CK. Essential for DDR applications

3) Multiple phase shifted clock outputs with phase offset of  45 degree, 90 degree or 180 degree. These are essential for clock recovery applications.

4) PLL lock signal. In other words lock detector of PLL.  
MDS & DR IM distortion IP3 IP3 Plot RX characterization Antenna Sel Cascade F PLL
Multi-chip de-skew application: Platform’s with multiple FPGA’s or ASIC’s requires synchronous and phase aligned clocks. This can be achieved by de-skewing clock distribution network.
What’s on chip clock de-skewing? This is a requirement to phase align the output clock of a PLL to its input reference clock. In other words, remove the delay on the clock caused by noise and process variations on chip. For this applications we need Delay Locked Loop (DLL) type PLL’s. With use of DLL type devices, we can sample data synchronously without skewing and limiting the useful period of the clock.
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