Home.Verilog.Digital Design.Digital Basics.Python.RF Basics.
Previous.
Next.
Custom Search

Legal Disclaimer

Chip Designing for ASIC/ FPGA Design engineers and Students
FULLCHIPDESIGN
Digital-logic Design...  Dream for many students… start learning front-end…

Legal Disclaimer

@TYH :- 4G LTE Long Term Evolution Tutorial, CloudComputing
PICS
Verilog Tutorial.
Get Noticed:- Submit your own content to be published on fullchipdesign.com

Send it to fullchip@gmail.com

Digital Basics Tutorial.
Universal Gates - OR from NAND
A (Input 1)
B (Input 2)
Z1(Interim Output)
Z2 (Interim output)
Final Output (equivalent to OR)
0
0
1
1
0
0
1
1
0
1
1
0
0
1
1
1
1
0
0
1
OR Gate
A (Input 1)
B (Input 2)
Z (Output)
0
0
0
0
1
1
1
0
1
1
1
1
NAND Gate
X (Input 1)
Y (Input 2)
Z (Output)
0
0
1
0
1
1
1
0
1
1
1
0
Steps to generate equivalent OR gate from NAND gate. From the truth-tables of NAND and OR gate above circuit is derived. It represents the required connectivity. The details are further discussed in truth table below.
Interview Questions. Main, FPGA, Digital Fundamentals
NAND universal AND from NAND Gate OR from NAND
PICS
LTE - Long Term Evolution topics from here
Equivalent OR GATE
NAND
NAND
X
NAND
Y
Z1
Z2