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Digital Basics Tutorial.
Register level and digital Microoperations.
Micro operations (or Microops) are arithmetic operations executed on contents of registers. Some examples are increment operation, decrement, right shift, left shift etc.  
Microoperations at Register Transfer Level.

Any digital microoperation follows the requirements below:-

1. Declare registers to load and store binary data.

2. Define a list of microoperations.

3. Declare control conditions for executing microoperations.

Microoperations are categorized further into following groups.

1. Aritmetic Microoperations.

2. Logic Microoperations.

3. Shift Microoperations.

Lets start our discussion of rtl and micro-operations with introductions to digital hardware operation :-
A digital hardware is a system of millions of logic blocks such as gates, flip-flops, memories etc. To implement any component inside a digital system requires basics understanding of its building blocks.

So to understand any hardware implementation its nice to know following.

1. Good understanding of digital gates and flip-flops.

2. Good understanding for Register Transfer Level or rtl .

 

 

Register transfer level:-  RTL is a specific term used by engineers to implement hardware  specifications using a languages such as Verilog or VHDL.
Registers :- Registers are group of flip-flops. Each flop within a register can store a digital value 1 or 0. The maximum number of values a register can hold is defined by the number of bits. An N bits register has N flip-flops and can store N binary values.  For example, a 4 bit register R1 can hold any  Value between ‘b0000 to ‘b1111. (‘b is for binary values).
Register transfer is related to moving the contents of one register to another register for specific arithmetic operations. For example: Moving contents of register R2 to register R1. This kind of transfers generally occurs when a control condition is triggered.  
If (R2 greater 10) then  R1 <– R2
Once the logic is coded, it needs to be simulated and synthesized to verify the correct implementation.
Refer following resources on FCD to understand RTL implementations.
1. RTL coding guidelines.
2. Verilog RTL example section.
3. Digital basics section.
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5 Steps required to build a functional FPGA load (valid for most EDA flows)

 

Arith Shft.